Backthinning of CMOS sensors provide certain advantages. These can include performance advantages such as improved light sensitivity as a result of improved effective fill factor and sensitivity to UV light or low energy electrons. Although processes that work with CCD sensors do not routinely transfer to the manufacture or structure of CMOS sensors, some do and are beneficial to consider and to use. For example, when properly passivated by a method such as that described in U.S. Pat. No. 5,688,715 which is applicable to CCDs, backthinned CMOS sensors also demonstrate high sensitivity to both UV light and low energy (˜0.5–20 keV) electrons. This property of backthinned CMOS sensors makes them particularly suitable for use in a vacuum environment as a video based image intensifier. U.S. Pat. No. 6,285,018 B1 details the use of CMOS sensors including back thinned imagers in an electron-bombarded configuration.
Some degree of fixed pattern noise generally and typically occurs in backthinned CMOS sensors. Sources include baseline sensor fixed pattern noise and fixed pattern noise that is introduced as a result of the back-thinning process. Back-thinned CMOS sensors are fabricated by taking a sensor designed for front side use and processing it to remove the silicon substrate. Processing for substrate removal includes subjecting the backside to an grinding processes until the substrate is sufficiently thinned after which the remaining substrate is subjected to chemical etching. Frontside CMOS die manufacturers often quote residual fixed pattern noise of <0.5%. Processing induced fixed pattern noise however, can be significantly greater than that seen on bare die. Fixed pattern noise (FPN) can result from both pixel offset and gain variations. A more detailed discussion of FPN as it relates to CMOS sensors can be found in U.S. Pat. No. 6,459,078. Measured values are highly dependent on test conditions that can be crafted to highlight FPN introduced via specific mechanisms. This invention is focused upon minimizing backside-thinning process induced FPN in CMOS imagers.
Properties shared by CMOS sensors place them in a class that is distinct from CCDs thereby necessitating new procedures and manufacturing approaches. It has been found in practice that CMOS imagers from a range of manufacturers are all highly stressed. This may result from the numerous metal and dielectric layers that characterize the modern CMOS imager. CCDs in contrast to CMOS imagers often employ only a couple metal layers and much thinner dielectric layers. CCDs tested to date do not exhibit the high levels of residual stress seen in CMOS imagers. Consequently, when CMOS die are thinned without a support structure bonded to the front side, the device curls and often breaks. The window-frame configuration, successfully applied to commercial backthinned CCDs, where a thin ring of thick substrate is left around an unsupported image array is impractical on commercially available CMOS sensors as a result of this residual stress. Accordingly CMOS die require bonding to a support structure on the front surface before thinning of the backside occurs. A preferred support material is Code 7740/Pyrex glass. Other useful materials are materials that have a thermal coefficient of expansion that generally matches the die. Typical bonding agents are thermal coefficient of expansion matched frit glass for vacuum compatible die or epoxy for less demanding applications. U.S. Pat. Nos. 6,168,965 and 6,169,319 describe a backside-illuminated sensor and method of manufacturing the same. These patents (U.S. Pat. Nos. 6,168,965 and 6,169,319) however, result in a sensor that has a transparent substrate which is bonded to the backside surface as a support and which thereby prevents direct access by impinging electrons to the backside surface. Yet, in order for a CMOS imager to be useful in the application of primary interest, the back surface of the sensor must be available and accessible. A method for forming a supported imager assembly suitable for the application of interest is detailed in U.S. Pat. No. 6,020,646.
An application of this invention of primary interest is an embodiment where the backthinned CMOS sensor is thinned to a point where the entire backside is removed leaving only the epitaxally grown silicon on the die. Backthinning may be performed along the entire surface or may be limited to the area of the pixel array. The CMOS sensor is then processed to lower back surface dark current generation and increase sensitivity. The sensor is then mounted in a vacuum directly opposing a photocathode, also in the vacuum, in a proximity-focused configuration as described in U.S. Pat. No. 6,285,018. This arrangement will be more fully discussed in connection with FIG. 1.
In attempting to operate the system shown in FIG. 1 at its best levels, as for example as a night vision imager, or in scientific studies involving low light levels, the images to be viewed are often captured at very low signal levels. When such images are displayed, residual fixed pattern noise associated with pixel offset is highlighted. At higher signal levels gain variance related FPN (fixed pattern noise) tends to dominate.